according to the published report, Nagare Labs, a Georgia Tech spinout backed by Playground Global, unveiled Z2RAM, a new memory technology designed to stack directly on AI accelerators.reported The company positions this capacitorless memory as a solution that combines the speed of SRAM with the density of DRAM.The company says this new memory type can be built with standard factory tools, avoiding expensive new equipment.The gain cell design enables non-destructive reads, eliminating DRAM write-back latency while leveraging DUV lithography for multi-layer stacking. This approach aims to address bandwidth bottlenecks in artificial intelligence chips without relying on traditional high-bandwidth memory architectures.
Evidence: reported
Gelsinger-backed Nagare Labs’ Z2RAM promises SRAM speed at DRAM densityaifleet-tomshardware
What was released or claimed
Nagare Labs claims its Gen 1 Z2RAM will achieve five times the density of SRAM using six stacked layers.reported The company states the technology offers fourteen times the speed of DRAM and consumes three times less read energy than SRAM. Founders’ papers indicate the memory cell holds data for over 300 seconds when tested at 85 degrees Celsius.reported The design uses two transistors and a shield, eliminating the capacitor found in DRAM cells.
Evidence: reported
Gelsinger-backed Nagare Labs’ Z2RAM promises SRAM speed at DRAM densityaifleet-tomshardware
Evidence: reported
Gelsinger-backed Nagare Labs’ Z2RAM promises SRAM speed at DRAM densityaifleet-tomshardware
Who it affects
AI chip manufacturers facing yield challenges with high-bandwidth memory may find this relevant. The report notes that some manufacturers plan to reduce HBM layer counts due to yield issues and heat constraints. Samsung’s zHBM, which stacks DRAM on processors, is planned for only about four layers partly because of thermal limits. Micron’s vHBM plans also include heat-spreading structures to manage thermal output.
What is still unknown
It remains unclear if Nagare Labs has produced commercial silicon or validated these projections at scale. The source material cites founders’ papers and projections rather than independent third-party testing or mass-production data. No timeline for general availability or specific partnerships with chipmakers was provided in the report. The actual yield rates and long-term reliability of the stacked layers are not detailed.
What to make of it
The technology attempts to decouple memory scaling from thermal constraints that limit current DRAM stacking. By avoiding capacitors and using a gain cell design, reads are non-destructive, avoiding the write-back overhead of DRAM. Nagare Labs states peak compute has grown 70 percent annually over three decades, while memory bandwidth grew only 20 percent.reported This gap suggests a structural need for higher bandwidth solutions that do not exacerbate heat issues.
Evidence: reported
Gelsinger-backed Nagare Labs’ Z2RAM promises SRAM speed at DRAM densityaifleet-tomshardware
What buyers should weigh
Buyers should consider the manufacturing advantage of using standard 300 mm tools with DUV lithography, which Nagare Labs says avoids the need for EUV.reported The company claims energy consumption will be well under a picojoule per bit.company claim However, the technology is currently described through projections and academic papers rather than shipped products. Decision-makers must weigh the potential density gains against the unproven nature of the six-layer stacking process.
Evidence: reported
Gelsinger-backed Nagare Labs’ Z2RAM promises SRAM speed at DRAM densityaifleet-tomshardware
Why it matters
- The use of standard DUV tools could lower manufacturing costs compared to EUV-dependent processes, potentially making high-density memory more accessible.
- Non-destructive reads eliminate DRAM write-back overhead, which may reduce latency and power consumption in AI inference workloads.
- Stacking memory directly on the die addresses the bandwidth gap between compute growth and memory bandwidth growth cited by the founders.
- Thermal limits on current HBM stacking suggest a market need for alternatives that do not cap logic heat output at 220 W/cm².
Topics: memory, AI chips, semiconductor manufacturing, Nagare Labs, HBM
Updated
Then / now / next
AI chips relied on HBM or stacked DRAM, which faced yield and thermal constraints limiting layer counts.
Nagare Labs unveiled Z2RAM, a capacitorless memory claiming SRAM speed at DRAM density using standard tools.
The industry will watch for independent validation of the six-layer stacking process and commercial adoption timelines.
Story timeline
- Then AI chips relied on HBM or stacked DRAM, which faced yield and thermal constraints limiting layer counts.
- 06 Nov 2026 Gelsinger-backed Nagare Labs’ Z2RAM promises SRAM speed at DRAM density
- Now Nagare Labs unveiled Z2RAM, a capacitorless memory claiming SRAM speed at DRAM density using standard tools.
- Next The industry will watch for independent validation of the six-layer stacking process and commercial adoption timelines.
The strongest doubt
Counterpoint from the sources
The source material notes that heat limits how hard logic can run when DRAM is stacked on top, and current HBM yields are challenging. Nagare’s claims are based on projections and papers, not independent commercial validation.
Ask the article
Local keyword search of this article; no generated answers.Did this article give you the evidence you needed?
Your choice stays on this device. No public tally.Terms in this story
Z2RAM
A capacitorless memory technology using two transistors and a shield to store data.
HBM
High-bandwidth memory, often stacked in layers to provide high data throughput to processors.
DUV
Deep ultraviolet lithography, a standard manufacturing process for semiconductor patterning.
SRAM
Static random-access memory, known for high speed but lower density compared to DRAM.
Questions readers ask
How does Z2RAM differ from traditional DRAM?
Z2RAM uses a capacitorless design with two transistors and a shield, whereas DRAM relies on a capacitor to store charge.
What manufacturing equipment does Nagare Labs use?
The company states it uses standard 300 mm tools with DUV lithography, avoiding the need for EUV equipment.
What are the projected performance metrics for Gen 1?
Nagare Labs projects five times SRAM density, fourteen times DRAM speed, and three times less read energy than SRAM.
Connected stories
Reading receipt
- Nagare Labs describes Z2RAM as a capacitorless cell using two transistors and a shield to store data.
- The company projects Gen 1 will offer five times the density of SRAM with six stacked layers.
- Manufacturing uses standard 300 mm tools with DUV lithography, avoiding the need for EUV equipment.
Still open: Has Nagare Labs demonstrated a working prototype with six stacked layers in a commercial setting?
Still open: What are the specific yield rates for the Z2RAM manufacturing process compared to traditional HBM?